The present invention relates to a peak voltage holding circuit and, more particularly, to a peak voltage holding circuit having holding characteristics with leakage characteristics obtained by a capacitor.
As a conventional peak voltage holding circuit, a circuit using a capacitor and an amplifier is available. In this circuit, an analog input voltage is applied to the capacitor through the amplifier having a rectifying function. If the analog input voltage is lower than a voltage held by the capacitor, the circuit is not rendered conductive because of the rectifying effect of the amplifier, and the capacitor keeps holding the previous voltage. In contrast to this, if the analog input voltage is higher than a voltage held by the capacitor, the circuit is rendered conductive because of the rectifying effect of the amplifier so as to charge the capacitor up to the level of the analog input voltage. With this operation, the peak value of the applied analog input voltages is held by the capacitor.
FIG. 1 is a circuit diagram showing a conventional peak voltage holding circuit using a capacitor and an amplifier.
Referring to FIG. 1, reference numeral 11 denotes a voltage holding capacitor; 13 and 14, amplifiers; 15 and 16, rectifiers; 10, an input terminal for an analog input voltage V.sub.X ; and 20, an output terminal for a peak voltage V.sub.P. The amplifiers 13 and 14 respectively constitute noninverting amplifying circuits each having a unitary gain. The output of the amplifier 14 is also connected to the inverting input terminal of the amplifier 13.
An operation of the conventional circuit shown in FIG. 1 will be described below. When the analog input voltage V.sub.X is applied to the input terminal 10, an output voltage V.sub.2 from the amplifier 13 becomes equal to the voltage V.sub.X. At this time, if the value of the output voltage V.sub.2 from the amplifier 13 is larger than that of a voltage V.sub.1 held by the voltage holding capacitor 11, the rectifier 16 is turned on to further charge the capacitor 11. In this case, since the capacitor 11 is charged through the rectifier 16, the capacitor 11 is charged to increase the voltage V.sub.1 by only a value obtained by subtracting a threshold voltage V.sub.T from the output voltage V.sub.2, i.e., V.sub.2 -V.sub.T.
In addition, since the output voltage V.sub.2 from the amplifier 13 is equal to the analog input voltage V.sub.X, and an output voltage V.sub.P from the amplifier 14 is equal to the voltage V.sub.1 held by the voltage holding capacitor 11, the output voltage V.sub.P from the amplifier 14 is equal to V.sub.X -V.sub.T.
An output from the amplifier 14 is fed back to the inverting input terminal of the amplifier 13. Therefore, a voltage to be applied to the inverting input terminal 13 is the output voltage V.sub.P from the amplifier 14, i.e., the voltage V.sub.X -V.sub.T. Since the analog input voltage V.sub.X is a voltage which is applied to the noninverting input terminal of the amplifier 13, the voltages applied to the noninverting and inverting input terminals of the amplifier 13 becomes unbalanced. The difference between the applied voltages is equal to the voltage V.sub.T. As a result, an output voltage from the amplifier 13 is changed due to the difference between the voltages applied to its noninverting and inverting input terminals. The change in output voltage from the amplifier 13 is fed back to the noninverting input terminal of the amplifier 13 through the amplifier 14. When a voltage applied to the noninverting input terminal of the amplifier 13 becomes equal to the analog input voltage V.sub.X, a balanced state is obtained and the change in output voltage from the amplifier 13 is stopped. Finally, the value of the output voltage V.sub.2 from the amplifier 13 becomes equal to V.sub.X +V.sub.T, and the voltage V.sub.1 held by the voltage holding capacitor 11 reaches the level of the voltage V.sub.2 to be equal to the analog input voltage. Therefore, if the peak value of the analog input voltage V.sub.X is a value V.sub.XP, the voltage V.sub.1 held by the capacitor 11 increases to the value V.sub.XP, and at the same time the output voltage V.sub.P from the amplifier 14 increases to the value V.sub.XP. At this time, the output voltage V.sub.2 from the amplifier 13 becomes a voltage V.sub.XP +V.sub.T due to the feedback effect from the amplifier 14 described above.
When the analog input voltage V.sub.X becomes smaller than the peak value V.sub.XP, an output voltage from the amplifier 13 becomes smaller than the voltage V.sub.XP +V.sub.T, and the rectifier 16 is reverse-biased to be nonconductive. Therefore, the change in input voltage is not transmitted to the voltage holding capacitor 11, and the capacitor 11 keeps holding the peak value V.sub.XP of the analog input voltage V.sub.X. Note that the rectifier 15 clamps an output from the amplifier 13 so as to prevent an output from the amplifier 13 from shifting to the negative side when the analog input voltage V.sub.X becomes negative.
When leakage characteristics are to be added to the holding characteristics of the above-described conventional peak voltage holding circuit, a resistor is connected in parallel with the voltage holding capacitor 11 so that charge accumulated in the capacitor 11 can be gradually discharged.
FIG. 2 shows such a leakage circuit. Referring to FIG. 2, reference numeral 21 denotes a resistor for constituting a leakage path of charge stored in the voltage holding capacitor 11; and 16, a diode for preventing reverse flow of charge, which is equivalent to the diode as the rectifier 16 in FIG. 1.
The resistance of the resistor 21 is determined such that a leakage time constant defined by the resistor 21 and the voltage holding capacitor 11 satisfies necessary leakage characteristics. The resistor 21 normally has a high resistance of 10.sup.6 .OMEGA. or more.
If, however, a peak voltage holding circuit having such a leakage circuit is to be formed into a monolithic IC, arrangement of a resistive element having a high resistance requires a special process, and the area of the circuit is increased. It is difficult to maintain the resistance of such a high-resistance resistor to be constant in terms of manufacture. For this reason, variation in leakage characteristics of products tends to occur. Therefore, such a leakage circuit is very difficult to design.